bit-string-accelerator
Synthesizable SystemVerilog accelerator for deterministic 64-bit-word bit addressing, FPGA and ASIC ready.
CUDA kernels, synthesizable RTL accelerators, hardware operating systems and flight computers.
Synthesizable SystemVerilog accelerator for deterministic 64-bit-word bit addressing, FPGA and ASIC ready.
FlashAttention systolic-array RTL with a SUBLEQ / phi-Born deterministic attention toolchain.
RV32IM-adjacent hardware/firmware sandbox: memory-mapped accelerator, bare-metal Zig driver and an analog sanity netlist.
Hardware operating system for RISC-V RV32IM and ARM Cortex-A8: bootloader, kernel, drivers and shell.
Composable Boolean GPU kernels in Rust over OpenCL.
Assembly language primitives for sovereign execution with verified instruction sequences.
GRiSP embedded hardware fleet with shadow execution and sovereign attestation.
Hilbert-4B architecture spec with CUDA kernels (RMSNorm, FlashAttn, SwiGLU, RoPE). Ampere GPUs, GGUF export.
NVIDIA GPU computing stack integration with CUDA, PTX, and kernel optimization tooling.
Browser spacecraft simulator and headless flight-model SDK.
x86_64 assembly reconstruction of TWIN-MARS agent. Direct syscalls, no libc dependencies.
Complete deterministic processor in pure Ada. 21 packages, RTX tensor engine, formal assertions, Lovelace design.
Apollo Guidance Computer rebuilt in 7 languages. Ada SPARK verification, Idris 2 proofs, Lean 4 zero-sorry.
Apollo Guidance Computer rebuilt by 7 AI systems with formal verification and quantum ignition circuits.
Zero-variance hardware trigger for ORTHO-32-T deterministic fabric. x86_64 assembly, SMMU shadow architecture.
Public API for ARM64 EL2 hypervisor, ORTHO-32-T chip fabric, formally verified AGI kernel.
Virtual processing-element machine: a systolic-array simulator.
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