file_name stringlengths 17 21 | text stringlengths 50 84.6k | license stringclasses 12
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module_777777315841.v | module memory #(parameter width=10 )(
input wire [7:0] datain,
output reg [7:0] dataout,
input wire clk,
input wire [width-1:0] addr,
input wire en,
input wire we
);
reg [7:0] mem[(2**width)-1:0];
`ifdef SIM_SKIPPROG
initial $readmemh("../../asm/out/ym09.hex", mem, (2**width)-4096,... | GNU General Public License v3.0 |
module_88888836098.v | module wideexpr_00701(ctrl, u0, u1, u2, u3, u4, u5, u6, u7, s0, s1, s2, s3, s4, s5, s6, s7, y);
input [7:0] ctrl;
input [0:0] u0;
input [1:0] u1;
input [2:0] u2;
input [3:0] u3;
input [4:0] u4;
input [5:0] u5;
input [6:0] u6;
input [7:0] u7;
input signed [0:0] s0;
input signed [1:0] s1;
input sign... | Apache License 2.0 |
module_88888836102.v | module isramsd_decoder(d,a,enbl);
input [2:0]a;
input enbl;
output reg [7:0]d;
always @(a)
begin
if(enbl==1)
begin
d[0] = !a[0] & !a[1] & !a[2];
d[1] = a[0] & !a[1] & !a[2];
d[2] = !a[0] & a[1] & !a[2];
d[3] = a[0] & a[1] & !a[2];
d[4] = !a[0] & !a[1] & a[2];
... | GNU General Public License v3.0 |
module_777777315852.v | module sep32 #(parameter width=10, parameter stg=5'd0)
(
input clk,
input cen,
input [width-1:0] mixed,
input [4:0] cnt,
output reg [width-1:0] slot_00,
output reg [width-1:0] slot_01,
output reg [width-1:0] slot_02,
output reg [width-1:0] slot_03,
output reg [width-1:0] sl... | GNU General Public License v3.0 |
module_777777315853.v | module sep32_cnt(
input clk,
input cen,
input zero,
output reg [4:0] cnt
);
reg last_zero;
always @(posedge clk) if(cen) begin : proc_cnt
last_zero <= zero;
cnt <= (zero&&!last_zero) ? 5'd1 : cnt + 5'b1;
end
endmodule | GNU General Public License v3.0 |
module_88888836109.v | module dlatch(
input d,
input en,
input rst,
output reg q
);
always@(d,en,rst)
begin
if(rst)
q<=0;
else
if(en)
q<=d;
end
endmodule | Apache License 2.0 |
module_88888836110.v | module expression_00870(a0, a1, a2, a3, a4, a5, b0, b1, b2, b3, b4, b5, y);
input [3:0] a0;
input [4:0] a1;
input [5:0] a2;
input signed [3:0] a3;
input signed [4:0] a4;
input signed [5:0] a5;
input [3:0] b0;
input [4:0] b1;
input [5:0] b2;
input signed [3:0] b3;
input signed [4:0] b4;
input signe... | Apache License 2.0 |
module_777777578001.v | module Serial2Parallel(
clk, rst_n, i_data, o_data_1, o_data_2, o_data_3, o_data_sig
);
input clk;
input rst_n;
input [N-1:0] i_data;
output wire [N-1:0] o_data_1;
output wire [N-1:0] o_data_2;
output wire [N-1:0] o_data_3;
output reg o_data_sig;
parameter N = 16;
reg [N-1:0]... | MIT License |
module_777777578002.v | module bits_combine(
i_data_r, i_data_g, i_data_b, o_data
);
input [7:0] i_data_r;
input [7:0] i_data_g;
input [7:0] i_data_b;
output wire [23:0] o_data;
assign o_data = {i_data_r, i_data_g, i_data_b};
endmodule | MIT License |
module_777777578003.v | module bits_fragment(
i_data, o_data_r, o_data_g, o_data_b
);
input [23:0] i_data;
output wire [7:0] o_data_r;
output wire [7:0] o_data_g;
output wire [7:0] o_data_b;
assign o_data_r = i_data[23:16],
o_data_g = i_data[15:8],
o_data_b = i_data[7:0];
endmodule | MIT License |
module_88888836114.v | module wideexpr_00275(ctrl, u0, u1, u2, u3, u4, u5, u6, u7, s0, s1, s2, s3, s4, s5, s6, s7, y);
input [7:0] ctrl;
input [0:0] u0;
input [1:0] u1;
input [2:0] u2;
input [3:0] u3;
input [4:0] u4;
input [5:0] u5;
input [6:0] u6;
input [7:0] u7;
input signed [0:0] s0;
input signed [1:0] s1;
input sign... | Apache License 2.0 |
module_777777578010.v | module Serial2Parallel(
clk, rst_n, i_data, o_data_1, o_data_2, o_data_3, o_data_sig
);
input clk;
input rst_n;
input [7:0] i_data;
output wire [7:0] o_data_1;
output wire [7:0] o_data_2;
output wire [7:0] o_data_3;
output reg o_data_sig;
reg [7:0] tmp_data_1;
reg [7:0] tmp_da... | MIT License |
module_88888836129.v | module partsel_00695(ctrl, s0, s1, s2, s3, x0, x1, x2, x3, y);
input [3:0] ctrl;
input [2:0] s0;
input [2:0] s1;
input [2:0] s2;
input [2:0] s3;
input signed [31:0] x0;
input [31:0] x1;
input signed [31:0] x2;
input [31:0] x3;
output [127:0] y;
wire [5:27] x4;
wire signed [5:29] x5;
wire [28:7] x6... | Apache License 2.0 |
module_777777315876.v | module jt95c061_timer(
input rst,
input clk,
input halt,
input [3:0] clk_muxin,
input [1:0] clk_muxsel,
input [3:0] ff_ctrl,
input [7:0] cntmax,
input run,
input da... | GNU General Public License v3.0 |
module_88888836134.v | module partsel_00133(ctrl, s0, s1, s2, s3, x0, x1, x2, x3, y);
input [3:0] ctrl;
input [2:0] s0;
input [2:0] s1;
input [2:0] s2;
input [2:0] s3;
input signed [31:0] x0;
input [31:0] x1;
input [31:0] x2;
input [31:0] x3;
output [127:0] y;
wire signed [26:7] x4;
wire [5:28] x5;
wire [31:0] x6;
wir... | Apache License 2.0 |
module_88888836135.v | module logic_cell(
input clk,
input rst_n,
input trig,
input in_t,
input in_r,
input in_b,
input in_l,
input in_i,
input en_i,
output out_t,
output out_r,
output out_b,
output out_l,
output out_o
);
reg [1:0] rot;
reg ff; ... | MIT License |
module_88888836138.v | module expression_00644(a0, a1, a2, a3, a4, a5, b0, b1, b2, b3, b4, b5, y);
input [3:0] a0;
input [4:0] a1;
input [5:0] a2;
input signed [3:0] a3;
input signed [4:0] a4;
input signed [5:0] a5;
input [3:0] b0;
input [4:0] b1;
input [5:0] b2;
input signed [3:0] b3;
input signed [4:0] b4;
input signe... | Apache License 2.0 |
module_777777315902.v | module RAM(
input clk,
input [9:0] addr,
input we,
input [7:0] din,
output reg [7:0] dout
);
reg [7:0] data [0:1023];
reg [9:0] we_addr;
always @(posedge clk) begin
we_addr <= addr;
dout <= data[addr];
end
always @(*) begin
if (we)
data[we_addr] <= din;
end
endmodule | GNU General Public License v3.0 |
module_777777315913.v | module k052591(
input pin_M12,
input pin_RST,
input pin_CS,
input pin_NRD,
input pin_START,
input pin_BK,
output reg pin_OUT0,
input [12:0] pin_AB,
inout [7:0] pin_DB,
output [12:0] pin_EA,
inout [7:0] pin_ED,
output pin_ERCS,
output pin_EROE,
output pin_ERWE,
input PIN21
);
reg rsts;
reg A195,... | GNU General Public License v3.0 |
module_777777315915.v | module CNT1(
input CLK,
input RESET,
input nLOAD, CEN1, CEN2,
input [3:0] D,
output reg [3:0] Q
);
always @(posedge CLK or posedge RESET) begin
if (RESET) begin
Q <= 4'd0;
end else begin
if (!nLOAD)
Q <= D;
else
if (CEN1 & CEN2) Q <= Q + 1'b1;
end
end
endmodule | GNU General Public License v3.0 |
module_777777315916.v | module CNT2(
input CLK,
input nLOAD, CEN1, CEN2,
input [3:0] D,
output reg [3:0] Q
);
always @(posedge CLK) begin
if (!nLOAD)
Q <= D;
else
if (CEN1 & CEN2) Q <= Q + 1'b1;
end
endmodule | GNU General Public License v3.0 |
module_777777315917.v | module CNT3(
input CLK,
input RESET,
input nLOAD, CEN1, CEN2,
input [4:0] D,
output reg [4:0] Q
);
always @(posedge CLK or posedge RESET) begin
if (RESET) begin
Q <= 5'd0;
end else begin
if (!nLOAD)
Q <= D;
else
if (CEN1 & CEN2) Q <= Q + 1'b1;
end
end
endmodule | GNU General Public License v3.0 |
module_777777315924.v | module FD2(
input nCK,
input D,
output reg Q,
output nQ
);
always @(negedge nCK)
Q <= #1 D;
assign nQ = ~Q;
endmodule | GNU General Public License v3.0 |
module_777777315926.v | module FD4(
input CK,
input D,
input PR, CL,
output reg Q = 1'b0,
output nQ
);
always @(negedge CK, negedge PR, negedge CL) begin
if (~PR)
Q <= #1 1'b1;
else if (~CL)
Q <= #1 1'b0;
else
Q <= #1 D;
end
assign nQ = ~Q;
endmodule | GNU General Public License v3.0 |
module_777777315937.v | module FS1(
input CK,
input SD,
output reg [3:0] Q
);
always @(negedge CK)
Q <= #1 {Q[2:0], ~SD};
endmodule | GNU General Public License v3.0 |
module_777777315938.v | module FS2(
input CK,
input [3:0] P,
input SD, L,
output reg [3:0] Q = 4'd0
);
always @(negedge CK)
begin
if (L)
Q <= #1 P;
else
Q <= #1 {Q[2:0], SD};
end
endmodule | GNU General Public License v3.0 |
module_777777315939.v | module FS3(
input CK,
input [3:0] P,
input SD, nL,
output reg [3:0] Q = 4'd0
);
always @(posedge CK, negedge nL) begin
if (!nL)
Q <= #2 P;
else
Q <= #1 {Q[2:0], SD};
end
endmodule | GNU General Public License v3.0 |
module_777777315944.v | module T2D(
input A, B,
input S2,
output X
);
assign X = S2 ? ~A : ~B;
endmodule | GNU General Public License v3.0 |
module_777777353314.v | module top
#(parameter param39 = (-(+((^~((8'hb6) * (8'h9e))) == (^~((8'hb6) >>> (7'h42)))))))
(y, clk, wire3, wire2, wire1, wire0);
output wire [(32'h19e):(32'h0)] y;
input wire [(1'h0):(1'h0)] clk;
input wire signed [(3'h6):(1'h0)] wire3;
input wire [(4'hc):(1'h0)] wire2;
input wire [(4'h8):(1'h0)] wire1;
... | GNU General Public License v3.0 |
module_777777315972.v | module jtbiocom_bus(
input [16:1] mcu_addr,
input [19:1] cpu_addr,
input mcu_wr,
input UDSWn,
input LDSWn,
input mcu_DMAn,
input [ 7:0] mcu_dout,
input [15:0] cpu_dout,
output reg [19:1] bus_addr,
outpu... | GNU General Public License v3.0 |
module_88888868688.v | module Sign_Extend
(
input [15:0] Sign_Ext_i,
output wire [31:0] Sign_Ext_o
);
assign Sign_Ext_o = { {16{Sign_Ext_i[15]}}, Sign_Ext_i};
endmodule | MIT License |
module_777777810160.v | module submuladd_2_stage_signed_8_bit_xor_reduction(
input signed [7:0] a,
input signed [7:0] b,
input signed [7:0] c,
input signed [7:0] d,
output [7:0] out,
input clk);
logic signed [15:0] stage0;
logic signed [15:0] stage1;
always @(posedge clk) begin
stage0 <= ((d - a) * b) + c;
stage1 <= stage0;
end
... | MIT License |
module_88888868691.v | module wideexpr_00215(ctrl, u0, u1, u2, u3, u4, u5, u6, u7, s0, s1, s2, s3, s4, s5, s6, s7, y);
input [7:0] ctrl;
input [0:0] u0;
input [1:0] u1;
input [2:0] u2;
input [3:0] u3;
input [4:0] u4;
input [5:0] u5;
input [6:0] u6;
input [7:0] u7;
input signed [0:0] s0;
input signed [1:0] s1;
input sign... | Apache License 2.0 |
module_88888868692.v | module gf180mcu_fd_sc_mcu7t5v0__aoi211_4( ZN, A2, A1, B, C );
input A1, A2, B, C;
output ZN;
wire A1_inv_for_gf180mcu_fd_sc_mcu7t5v0__aoi211_4;
not MGM_BG_0( A1_inv_for_gf180mcu_fd_sc_mcu7t5v0__aoi211_4, A1 );
wire B_inv_for_gf180mcu_fd_sc_mcu7t5v0__aoi211_4;
not MGM_BG_1( B_inv_for_gf180mcu_fd_sc_mcu7t5v0__aoi211_4... | Apache License 2.0 |
module_777777353321.v | module top (y, clk, wire3, wire2, wire1, wire0);
output wire [(32'h79):(32'h0)] y;
input wire [(1'h0):(1'h0)] clk;
input wire [(4'h9):(1'h0)] wire3;
input wire signed [(3'h7):(1'h0)] wire2;
input wire signed [(4'h9):(1'h0)] wire1;
input wire [(4'hc):(1'h0)] wire0;
wire [(4'h8):(1'h0)] wire14;
wire [(5'h1... | GNU General Public License v3.0 |
module_777777316058.v | module jtcps1_obj_table(
input rst,
input clk,
input pxl_cen,
input obj_dma_ok,
output reg busreq,
input busack,
input [15:0] vram_base,
output [17:1] vram_addr,
input [15:0] vram_da... | GNU General Public License v3.0 |
module_777777316076.v | module jtcps15_z80buslock(
input clk,
input rst,
input cen8,
output reg busrq_n,
input busak_n,
input buse_n,
input [23:12] m68_addr,
input m68_buswen,
output z80_buswn,
output reg m68_busakn
);
paramete... | GNU General Public License v3.0 |
module_88888868709.v | module wideexpr_00371(ctrl, u0, u1, u2, u3, u4, u5, u6, u7, s0, s1, s2, s3, s4, s5, s6, s7, y);
input [7:0] ctrl;
input [0:0] u0;
input [1:0] u1;
input [2:0] u2;
input [3:0] u3;
input [4:0] u4;
input [5:0] u5;
input [6:0] u6;
input [7:0] u7;
input signed [0:0] s0;
input signed [1:0] s1;
input sign... | Apache License 2.0 |
module_777777316106.v | module jtdd_dip(
input clk,
input [31:0] status,
input dip_pause,
input dip_test,
input dip_flip,
output turbo,
output reg [ 7:0] dipsw_a,
output reg [ 7:0] dipsw_b
);
wire dip_upright = 1'b0;
wire [1:0] ... | GNU General Public License v3.0 |
module_777777810161.v | module submuladd_2_stage_signed_9_bit(
input signed [8:0] a,
input signed [8:0] b,
input signed [8:0] c,
input signed [8:0] d,
output [8:0] out,
input clk);
logic signed [17:0] stage0;
logic signed [17:0] stage1;
always @(posedge clk) begin
stage0 <= ((d - a) * b) + c;
stage1 <= stage0;
end
assign out = s... | MIT License |
module_777777316151.v | module jtfround_draw#( parameter
CW = 19,
PW = 8,
KEEP_OLD = 0,
SWAPH = 0
)(
input rst,
input clk,
input draw,
output reg busy,
input [CW-1:0] code,
input [ 8:0] xpos,
input ... | GNU General Public License v3.0 |
module_77777748299.v | module IBUFG_SSTL3_II (O, I);
output O;
input I;
buf B1 (O, I);
endmodule | Apache License 2.0 |
module_777777316207.v | module jt74283(
input [3:0] a,
input [3:0] b,
input cin,
output [3:0] s,
output cout
);
assign #2 {cout,s} = a+b+cin;
endmodule | GNU General Public License v3.0 |
module_777777316240.v | module pocket_dump(
input scal_vs,
input [31:0] frame_cnt
);
`ifdef DUMP
`ifdef DUMP_START
always @(posedge scal_vs) if( frame_cnt==`DUMP_START ) begin
`else
initial begin
`endif
$dumpfile("test.lxt");
`ifdef DEEPDUMP
$display("NC Verilog: will dump all sig... | GNU General Public License v3.0 |
module_777777316285.v | module pocket_dump(
input scal_vs,
input [31:0] frame_cnt
);
`ifdef DUMP
`ifdef DUMP_START
always @(posedge scal_vs) if( frame_cnt==`DUMP_START ) begin
`else
initial begin
`endif
$dumpfile("test.lxt");
`ifdef DEEPDUMP
$display("NC Verilog: will dump all sig... | GNU General Public License v3.0 |
module_777777353380.v | module top
#(parameter param21 = (((^(((8'hb7) + (8'ha7)) ? {(7'h41), (8'ha9)} : (8'ha2))) ? (|((+(8'hb3)) ? ((8'hba) - (8'h9d)) : {(8'hb2), (8'hbe)})) : (^~((~|(7'h43)) ? (&(8'hbd)) : ((8'hbf) > (8'hab))))) >> (&(~|(8'ha5)))))
(y, clk, wire4, wire3, wire2, wire1, wire0);
output wire [(32'ha9):(32'h0)] y;
input wir... | GNU General Public License v3.0 |
module_777777578455.v | module axis_adapter #
(
parameter S_DATA_WIDTH = 8,
parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8),
parameter S_KEEP_WIDTH = ((S_DATA_WIDTH+7)/8),
parameter M_DATA_WIDTH = 8,
parameter M_KEEP_ENABLE = (M_DATA_WIDTH>8),
parameter M_KEEP_WIDTH = ((M_DATA_WIDTH+7... | MIT License |
module_77777748300.v | module IBUFG_SSTL3_II_DCI (O, I);
output O;
input I;
buf B1 (O, I);
endmodule | Apache License 2.0 |
module_777777578459.v | module axis_broadcast #
(
parameter M_COUNT = 4,
parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
parameter LAST_ENABLE = 1,
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST... | MIT License |
module_777777578460.v | module axis_cobs_decode
(
input wire clk,
input wire rst,
input wire [7:0] s_axis_tdata,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire s_axis_tuser,
output wire [7:0] m_axis_tdata,
... | MIT License |
module_777777578462.v | module axis_crosspoint #
(
parameter S_COUNT = 4,
parameter M_COUNT = 4,
parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
parameter LAST_ENABLE = 1,
parameter ID_ENABLE = 0,
parameter ID_W... | MIT License |
module_777777578464.v | module axis_fifo #
(
parameter DEPTH = 4096,
parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
parameter LAST_ENABLE = 1,
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
par... | MIT License |
module_777777578466.v | module axis_frame_join #
(
parameter S_COUNT = 4,
parameter DATA_WIDTH = 8,
parameter TAG_ENABLE = 1,
parameter TAG_WIDTH = 16
)
(
input wire clk,
input wire rst,
input wire [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata,
... | MIT License |
module_777777578467.v | module axis_frame_len #
(
parameter DATA_WIDTH = 64,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
parameter LEN_WIDTH = 16
)
(
input wire clk,
input wire rst,
input wire [KEEP_WIDTH-1:... | MIT License |
module_777777578468.v | module axis_frame_length_adjust #
(
parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH = 8,
... | MIT License |
module_777777578470.v | module axis_ll_bridge #
(
parameter DATA_WIDTH = 8
)
(
input wire clk,
input wire rst,
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire ... | MIT License |
module_777777578471.v | module axis_mux #
(
parameter S_COUNT = 4,
parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH... | MIT License |
module_777777316330.v | module pocket_dump(
input scal_vs,
input [31:0] frame_cnt
);
`ifdef DUMP
`ifdef DUMP_START
always @(posedge scal_vs) if( frame_cnt==`DUMP_START ) begin
`else
initial begin
`endif
$dumpfile("test.lxt");
`ifdef DEEPDUMP
$display("Verilog sim will dump all sig... | GNU General Public License v3.0 |
module_777777578475.v | module axis_rate_limit #
(
parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
parameter LAST_ENABLE = 1,
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
para... | MIT License |
module_777777578476.v | module axis_register #
(
parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
parameter LAST_ENABLE = 1,
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter D... | MIT License |
module_777777578477.v | module axis_srl_fifo #
(
parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
parameter LAST_ENABLE = 1,
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter D... | MIT License |
module_777777578478.v | module axis_srl_register #
(
parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
parameter LAST_ENABLE = 1,
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
paramet... | MIT License |
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